1. Field of the Invention
The invention relates to the field of metal-oxide-semiconductor (MOS) electrically programmable and electrically erasable read-only memories (EEPROMs) having floating gates and to electrically programmable read-only memories (EPROMs).
2. Prior Art
The most commonly used EPROM cell has an electrically floating gate which is completely surrounded by insulation and generally disposed between source and drain regions. In early versions of these cells, charge is injected through the insulation by avalanche injection such as the device described in U.S. Pat. No. 3,660,819. Later versions of EPROMs relied on channel injection for charging the floating gate as shown in U.S. Pat. Nos. 4,142,926; 4,114,255 and 4,412,310. These EPROMs are erased by exposing the array to ultraviolet radiation.
Electrically erasable EPROMs (EEPROMs) are also commercially available. In some cases, charge is placed into and removed from a floating gate by tunneling th charge through a thin oxide region formed on the substrate (see U.S. Pat. No. 4,203,158). In other instances, charge is removed through an upper electrode (see U.S. Pat. No. 4,099,196).
EPROMs are most often removed from their printed circuit boards for both erasing and programming. A programming device (e.g., commercially available programmer) is used for programming the cells. This device controls the voltage and current applied to the cells during programming. Current and voltage must be regulated to assure that too much current/voltage is not applied to the cell for reasons which are described later in the application. This regulation is easily accomplished within a programmer, since, for example, the voltages within the programmer can be calibrated when the device is manufactured and/or stable voltage regulations are well-known.
EEPROMs are typically programmed and erased while installed in the same circuit (e.g., printed circuit board) used for reading data from the memory. That is, a separate programming device is not used. Since these devices are typically programmed by tunnelling, the control, particularly of current, is not as critical as with EPROMs.
A problem arises with flash EPROMs where the memories are programmed through on-chip circuitry, that is, where a separate programming device is not used. The current/voltage for programming the cells must be controlled and this control must be consistent from chip-to-chip. The present invention is directed toward a load line for providing this control.
The closest prior art known to Applicant is described in an article entitled "A 256-K Bit Flash E2PROM Using Triple--Polysilicon Technology", IEEE Journal of Solid-State Circuits, Vol SC22, No. 4, Aug. 1987.